Analysis of Parallelism and Deadlocks in Distributed-Time Logic Simulation

This paper explores the suitability of the Chandy-Misra algorithm for digital logic simulation. We use four realistic circuits as benchmarks for our analysis, including the vector-unit controller for the Titan supercomputer from Ardent. Our results show that the average number of logic elements available for concurrent execution ranges from 10 to 111 for the four circuits, with an overall average of 68. Although this is twice as much parallelism as that obtained by traditional event-driven algorithms for these circuits, we feel it is still too low. One major factor limiting concurrency is the large number of global synchronization points --“deadlocks” in the Chandy-Mrsra terminology -that occur during execution. Towards the number of deadlocks, the paper % oal of reducing the eadlocks that occur during digital logic simulation. 8 resents a classification of the types of our different terms of circuit structure. Usin YEi s are identified and described intuitively in these deadlock occurrences an% domain specific owledge, we propose methods for reducing give some preliminary results regarding the effectiveness of these methods. For one of the benchmark circuits, the use of the {\em all} deadlocks and increased the average arallelism from i roposed techniques eliminated 0 to 160. We believe that the use of such domain knowledge will make trle Chandy-Misra algorithm significantly more effective than it would be in its generic form, We also present some preliminary results comparing the performance of the Chandy-Misra algorithm versus a parallel event-driven algorithm.